Fast-lock Hybrid PLL Combining Fractional- & Integer-N Modes of Di®ering Bandwidths

We report a single-loop PLL that operates in a wide-bandwidth, fractional-N mode (with no fractional spur reduction scheme) during transient but in a narrow-bandwidth, integer-N mode during phase lock. This hybrid PLL, as an extension of the conventional fast-lock PLL (that shifts only its bandwidth while retaining the same frequency division mode), simultaneously achieves the fastlock advantage of the fractional-N PLL and design simplicity of the integer-N PLL, bringing unique bene ̄ts. It also enables a new, more digital protocol to execute bandwidth switching. The hybrid PLL concept is a±rmed by a 2.4-GHz, 1-MHz resolution CMOS hybrid PLL prototype of integer-N -level design-simplicity, which exhibits a 20-1s lock time for a 64-MHz frequency step, outperforming its ̄xed integer-N operation by a factor of 4.